Besides, the compensation capacitor C m used in this design is very small, only 1.8 pF. When the value of the load capacitor C L is large, in order to compensate for non-dominate pole, g m f 2 needs to be set to a larger value, resulting that the product of M and N is very large.
Therefore, the proposed LDO without an off-chip capacitor can be used for some digital and memory sub-blocks while an additional off-chip capacitor can be embedded to power up some noise-sensitive analog subblocks. off-chip capacitor and capacitor-free condition.
In addition, the area of the compensation capacitance is very large compared with that of the transistor. Therefore, the on-chip capacitor is also usually considered in the performance of LDO. As a standard to measure the performance of LDO, there are many expressions for FoMs.
It uses capacitor C m for miller compensation. Among them, a high-gain RFC is used as an error amplifier , M 1, M 2, M 3, and M 4 constitute the input stage, and the quiescent current flowing through them is equal. The power transistor M p uses PMOS.
A CMOS LDO, which has the capacitor-free feature, based on the architecture of a three-stage amplifier and DFC frequency compensation, has been presented. The advanced structure, the-oretical analysis on the stability, and the experimental results have been provided.
Under such circumstance without the off-chip capacitor, ESR does not exist. Moreover, the second and third poles are pushed to frequencies that are higher than the unity-gain frequency of loop gain due to a large . The transfer function is given by 90 . However, parasitic poles and zeros will degrade the phase margin.
This off-chip capacitor is the main obstacle to fully integrating LDOs in system-on-chip designs. As a result, low-voltage high-stability and fast-transient LDOs with, preferably, capacitor-free …
The paper helps the power electronics development and design engineer in the design and performance evaluation procedure of dc bus capacitors for three-phase inverters. This paper …
This paper presents circuit design methodologies to enhance the electromagnetic immunity of an output-capacitor-free low-dropout (LDO) regulator.
To reduce the dependence on expert knowledge in the design process, Park et al. [39] proposed a DRL-based decoupling capacitors design method for silicon interposer …
In response to this situation, this paper first introduces the resonance-free concept as well as the corresponding index. Based on it, the methods to configure the shunt capacitors into the two …
This paper presents a design methodology for LDOs with NMOS pass transistors, focusing on the PSR enhancement techniques, including both the DC PSR and …
In this paper we will analyze some of the popular PDN design methods by first comparing their performances based on lumped self-impedance profiles. Later we look at some of the important
In this paper, a low-power capacitor-free LDO with novel slew rate enhancement is proposed. Employing the method of capacitive-coupling to provide large dynamic current, LDO with this …
This paper presents design methods to configure a shunt capacitor as a C-type filter or a third-order high-pass filter with guaranteed resonance-free performance.
In this research, a high-efficiency design method of the capacitive MEMS accelerometer is proposed. As the MEMS accelerometer has high precision and a compact …
This paper presents design methods to configure a shunt capacitor as a C-type filter or a third-order high-pass filter with guaranteed resonance-free performance. The …
This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred …
Then, a thorough algorithm for dc bus capacitor design is provided. The application of the proposed design method is demonstrated through several design examples. Overall, the paper …
This paper presents a design methodology for LDOs with NMOS pass transistors, focusing on the PSR enhancement techniques, including both the DC PSR and …
In electrical engineering, a capacitor is a device that stores electrical energy by accumulating electric charges on two closely spaced surfaces that are insulated from each other. The …
This off-chip capacitor is the main obstacle to fully integrating LDOs in system-on-chip designs. As a result, low-voltage high-stability and fast-transient LDOs with, preferably, capacitor-free …
Capacitors are among the simplest of electronic components – in theory – but the practical implementation is becoming more complex, says Christian Merkel. ... dielectric …
Design of capacitor-less LDO applied to low power supply with high-precision bandgap
The design method of high-resolution capacitor arrays was proposed to improve the precision of successive approximation register (SAR) analog-to-digital converters (ADCs) …
From Eqs. (2-4) and (2-5), it can be seen that in addition to the low-frequency fluctuating power Q 1 (t) and Q 2 (t) in the system, there is also the power Q e (t) generated by …
This paper presents design methods to configure a shunt capacitor as a C-type filter or a third-order high-pass filter with guaranteed resonance-free performance. The …
Fig. 1. Switching transient when two capacitors are connected in parallel to transfer the energy. (a). Charge balance circuit. (b). Equivalent circuit. (c) Charge current at …
Configuring a shunt capacitor as a detuned C-type filter is an effective way to mitigate the capacitor caused harmonic resonance. A design method has been developed …